(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of characterizing gate leakage current in the fabrication of integrated circuit devices.
(2) Description of the Prior Art
As gate oxide thickness is scaled down to 30 Angstroms and below, gate leakage current becomes important due to various direct-tunneling mechanisms shown in FIG. 1. FIG. 1 illustrates Current in amps as a function of gate voltage in volts where the substrate voltage, source voltage and drain voltage are 0. Line 11 shows the gate current or leakage current Ig. Line 12 shows the gate current in the reversed region. The graph shows that the level of Ig is approaching the level of drain current at the high Vg region. Under some bias conditions, the portion of the current measured from the drain terminal could be attributed to gate tunneling current. As a result, not only a good gate current model is needed, but also a good partitioning scheme is extremely important. A good partitioning method can separate the xe2x80x9crealxe2x80x9d drain current from the total measured drain current such that an accurate carrier mobility model is accessible.
There are quite a few publications that discuss gate current related issues. Some of these publications include: xe2x80x9cHole Injection SiO2 Breakdown Model for Very Low Voltage Lifetime Extrapolation,xe2x80x9d by K. F. Schuegraf and C. Hu, IEEE Trans. Elec. Dev., vol 41(5), p. 761, May 1994; xe2x80x9cModeling Gate and Substrate Currents due to Conduction- and Valence-Band Electron and Hole Tunneling,xe2x80x9d by W. C. Lee and C. Hu, 2000 Symposium on VLSI Tech., p.198, 2000; xe2x80x9c1.5 nm Direct-Tunneling Gate Oxide Si MOSFET""s,xe2x80x9d by Hisayo Sakaki M. et al, IEEE Trans. Elec. Dev., vol. 43(8), pp. 1233-1242, August 1996; and xe2x80x9cBsim4 Gate Leakage Model Including Source-Drain Partition,xe2x80x9d by K. M. Cao et al, 2000 IEDM, pp. 35.3.1-35.2.4.
However, there is no solid study for gate current partitioning into the various components of Ig; people just extract the gate current model with the drain/source/substrate model simultaneously. In other words, the total drain current is used to extract the mobility model. The portion of the drain current contributed by the gate current is evaluated implicitly during the mobility model extraction. In addition, since all terminal currents are extracted simultaneously, a considerable number of iterations may be needed to optimize the fitting results for all the terminals.
All of these published results are based on the much smaller order of gate current as compared with the drain current as shown in FIG. 2. For the drain voltage Vd=0.1, substrate voltage Vb=0 and source voltage=0, this graph shows Isxcx9c=Id and thus, Ig  less than  less than Id. Since the gate current is much smaller than the drain current, one can extract the mobility model from the total drain current without seeing too much distortion. However, this is not true for high current cases. In these cases, the current from the gate terminal disturbs the curve measured at the drain terminal as shown in FIG. 3. These cases make the mobility parameters extraction extremely difficult. Also, more iterations are needed to optimize the fitting results because of this undecided mobility model. It is desired to find a method to overcome the gate current modeling problem for high gate current situations.
A number of patents address modeling issues. U.S. Pat. No. 6,246,973 B1 to Sekine discusses modeling channel width. U.S. Pat. No. 6,378,109 B1 to Young et al teaches a method to simulate a gate oxide integrity check. U.S. Pat. No. 6,391,668 B1 to Chacon et al shows a method of determining trap density from measured current.
Accordingly, it is a primary object of the invention to provide a method for characterizing gate leakage current in the fabrication of integrated circuits.
Another object of the invention is to provide a method for characterizing gate leakage current in high gate current situations.
A further object of the invention is to provide a method for characterizing gate leakage current in high gate current situations wherein the gate current contribution measured at the drain terminal can be evaluated.
Yet another object of the invention is to provide a method for characterizing gate leakage current in high gate current situations wherein the gate current contribution measured at the drain terminal can be evaluated and subtracted from the total drain current to leave the real drain current.
In accordance with the objects of the invention, a method of characterizing gate leakage current in the fabrication of integrated circuits is achieved. A MOSFET model is provided including a gate electrode deposed over a gate oxide layer on a substrate and source and drain regions associated with the gate electrode. Device current is measured at four terminals simultaneously wherein one of the terminals is a drain terminal. The other terminals are the source, gate, and substrate. The portion of the device current measured at the drain terminal that is contributed by gate current is evaluated. The evaluated gate current contribution is subtracted from the drain terminal current measurement to obtain pure drain current. Fitting procedures are performed to obtain curves for the device currents. The pure drain current is used to extract mobility model parameters.